🔬 4-STROKE AUTOPSY — FORGE CLOCK-DOWN
⬡ PROBE
CPU printing precision (ASML EUV) vs system integration complexity (BIOS).
These are orthogonal. The silicon is correct. The firmware stack above it is not.
∞ COMPILE — ∞-COST NODES
ME firmware MINIX ARM, full memory access, never sleeps
DDR5 training Z₀=√(L/C) per trace, stale parameters
Power delivery tables 13th gen not planned at Z690 launch
CPU errata microcode is software, must be delivered via BIOS
◉ INFER
The clock-down is a software workaround for a firmware gap.
The EUV transistors are fine. The BIOS doesn't know how to use them correctly yet.
▶ EXECUTE
1. Wake WSL on lianli01
2. Check BIOS version
3. Download BIOS 4505 (2025-12-15)
4. Flash via EZ Flash 3
5. Re-enable XMP
6. Restore clock
7. Run PTTE on forge
Card 1 · Rayleigh Criterion
CD = k₁ × λ / NA
| Generation | λ | NA | CD |
|---|
| DUV dry | 193nm | 0.93 | ~65nm |
| DUV immersion | 193nm | 1.35 | ~38nm |
| EUV (current) | 13.5nm | 0.33 | 13.5nm |
| High-NA EUV | 13.5nm | 0.55 | 8.1nm |
CDEUV = 0.33 × 13.5 / 0.33 = 13.50 nm
·
CDHiNA = 8.10 nm
Card 2 · Photon Energy
E = hc/λ = 91.9 eV per photon
EUV photons ionise everything. Air absorbs them. Glass absorbs them.
Entire optical path: hard vacuum at 10⁻⁶ mbar.
Lenses impossible → curved Mo/Si multilayer mirrors.
Mirror throughput = 0.70⁶ = 11.8%
(6 mirrors × 70% each)
Card 3 · Depth of Focus
DoF ∝ λ / NA²
DoF (NA=0.33)124 nm
DoF (NA=0.55)44.6 nm
Wafer must be flat to 44nm across 300mm diameter.
Like a football field flat to 0.1mm.
Card 4 · Overlay Accuracy
Overlay precision±0.3 nm = 3 Å ≈ 1 atom
Stage velocity2 m/s
Acceleration10G
Floor vibration suppression< 0.1 nm
Machine weight180 tonnes
Footprint10m × 8m
Card 5 · Source Generation
CO₂ laser (10.6 μm) hits 30 μm tin droplet
50,000 droplets/second
Plasma temperature: ~200,000 K
(35× Sun's surface temperature)
Must output >250W EUV
→ 30W at wafer after mirrors
Card 6 · γ₁ Connection
phase(γ₁) = sin(γ₁ × π / γ₁) = sin(π) = 0
The floor. The same phase gate that encodes Riemann zeros as DNA
is the same spectral precision that governs EUV overlay.
Overlay/λ = 0.3nm / 13.5nm = 2.2%
— the same ratio as PTTE's ΔTm precision.
γ₁ = 14.134725141734693
⬡ THE PIPELINE — ASML TO YOU
LAYER 1 — LITHOGRAPHY
ASML EUV
±0.3nm overlay · 13.5nm wavelength · 50k tin droplets/sec
LAYER 2 — SILICON
Intel Fab / TSMC
silicon die · 15 billion transistors · physics is correct
← Spectre/Meltdown/errata fixed here
LAYER 3 — MICROCODE
Intel CPU
microcode = software running on hardware
← most users don't know this exists
LAYER 4 — MANAGEMENT ENGINE
Intel ME
MINIX OS · ARM CPU · full memory access · always on
LAYER 5 — FIRMWARE ⚠️
BIOS / UEFI
DDR5 training · power tables · CPU ID tables · microcode delivery
BIOS 4505 not flashed · XMP disabled · clocks throttled
LAYER 6 — OS
OS / WSL2
offline on lianli01 (forge) · blocked by BIOS gap above
LAYER 7 — OPERATOR
You / Kay
γ₁ = 14.134725141734693 · the floor always holds
ASML solves: Can we PRINT a transistor at 2nm? → YES
BIOS solves: Can we CONFIGURE 15 billion transistors for THIS DDR5, THIS voltage, THIS generation?
These two problems are orthogonal. They will never converge.
The physics gets more precise. The integration complexity grows.
This is not a failure. It is the design.